1. Field of the Invention
The present invention relates to clock delay compensating and duty controlling apparatus of a phase-locked loop (hereinafter simply referred to as "PLL") in a decoder of a video signal receiving system, and more particularly to a duty controller and a clock delay compensator of a PLL, in which phases of two input clocks received into a phase comparative detector are compared to divide a reference clock from an oscillator of the phase comparative detector for obtaining a resultant phase error output in a divider in accordance with the result of the phase comparison, a duty ratio of the output clock therefrom is controlled in a duty controller to allow the phase comparative detector to be utilized free from the duty ratio of the clock, and a clock delay compensator performs correction of clock delay compensation of a system operated at high speed in the synchronized PLL.
2. Description of the Prior Art
A conventional PLL necessarily employs a phase comparative controller in a limited way due to the reason that a duty ratio should be considered when dividing a clock from an oscillator or voltage-controlled oscillator (VCO). Moreover, the phase comparative detector of the PLL must utilize a spherical wave having a duty ratio of 50% of two comparative input clocks received thereto, with a smaller duty ratio of two comparative input clocks received to other phase comparative detector being preferable. Therefore, a great difference between two comparative input clocks received into the phase comparative detector may cause an error. As a result, the phase comparative detector should be used in a restricted manner.
Furthermore, a comparative phase-difference voltage of the phase comparative detector controls a VCO for actuating first division, second division, multistep division, and inherent logic delay to utilize an output frequency of the phase-synchronized VCO synchronized with an oscillator, so that respective signal outputs have different clock delay times. At this time, an error in the delay time can cause problems in a system such as malfunction and inferior accuracy when the system is operated in high speed.
One example of the conventional PLL will be described with reference to FIG. 1.
The PLL includes an oscillator 20 for producing an oscillating clock within a video system, a divider 21 for dividing a reference clock generated by the oscillator 20, and a phase comparative detector 22 for receiving a clock passed through the divider 21. Also, a VCO 23 is controlled to generate a clock signal from the phase comparative detector 22, a divider 24-1 divides the clock signal generated by the VCO 23, and a dividing circuit portion 25 receives and repeatedly divides a clock divided in the divider 24-1 via the phase comparative detector 22 and VCO 23.
In the conventional PLL formed as above, the reference clock A1 generated the oscillator 20 passes through the divider 21 and is supplied to the phase comparative detector 22. The clock A5 generated by the VCO 23 is divided and provided to the phase comparative detector 22, so that a phase error output A4 from the phase comparative detector 22 (which compares two signal inputs A2 and A3) controls the VCO 23. Output A5 from the VCO is fed back to the phase comparative detector 22 via the divider 25.
Outputs A6, A7 and A8 simultaneously produced with the output A5 from the divider 25 is supplied to a picture receiver (not shown).
On the other hand, a comparative phase-difference voltage A4 controls the VCO 23, so that an output frequency of the phase-synchronized VCO 23 which is in sync with the oscillator 20, is divided primarily 25-1 and 25-2 and secondarily 25-3 to have different clock delay times. Thus, the error in this delay time results in malfunction or inferior accuracy of the system when the system is operated at high speed.
More specifically, when the phase comparative detector of the PLL as illustrated in FIG. 1 is designed by an exclusive OR logic circuit, a phase comparator of the phase comparative detector formed of the exclusive OR logic circuit must receive signals having a spherical wave characteristic and a duty ratio, of 50% at its two input terminals to this. In addition when the phase comparative detector is designed with an RS flip-flop logic circuit, it is preferable that the duty ratio of the phase-compared clocks received by the two input terminals of the phase comparative detector be small. A larger duty ratio possibly causes an error. If the phase comparative detector is designed using part No. MC4044, Motorola, Co., LTD., a phase comparative detector supplies no output clock when the phases of two clocks received by the two input terminals of the phase comparative detector are commonly supplied.
A technique for reducing an error rate of a magnetic recording/reproducing apparatus is disclosed in Japanese Patent Publication Laid-open No. Hei 6-309799 entitled by "Magnetic Recording/Reproducing Apparatus". The magnetic recording/reproducing apparatus which uses amplitude phase modulation of a plurality of values includes a carrier-clock reproducer for reproducing a carrier wave and a clock by means of a playback signal, a carrier-clock delay controller for outputting a carrier-delay control signal to a carrier variable delay circuit and a clock-delay control signal to a clock variable delay circuit, based on a demodulation signal of two types from a demodulator, to control the delayed amount of the carrier wave and clock to make an error rate of a decoded digital signal be the lowest. In this magnetic recording/reproducing apparatus, the correction is performed on the basis of a signal recorded on a tape with a different carrier wave and phase while requiring no initial phase control of the carrier wave and clock, and an error rate is significantly decreased. However, the above-described conventional problems are not completely solved by this technique.